40 uur per week
Startdatum op 21 augustus
310 Dagen geleden

FPGA Developer

Searching for someone who has experience with VHDL designs

Job description:

  • Take over the existing VHDL design from a still present FPGA engineer This design builds in Xilinx Vivado
  • Integrate the updated Audinate IP core to support 128×128 audio channels
  • Create a core to allow other enginering teams to add their own FPGA configuration
  • Support the SW team to get the solution fully working and tested
  • Fix detected bugs both on the existing as the new design


  • Multiple years experience in VHDL designs
  • Must have experience with the Xilinx tool chain since this is a time limited assignment
  • Experience with designs which require close cooperation with SW engineers
  • Clear communicator both verbal as in writing 
  • Pro-active with a quality mindset